This invention relates to semiconductor memory devices, and more particularly to dynamic memory cells using storage capacitors with tantalum oxide dielectric.
Semiconductor memory devices of the dynamic read/write type traditionally are constructed using one-transistor cells with MOS storage capacitors which have silicon oxide dielectric. Over the past ten years, these devices have been made in progressively higher bit density and small cell size; in 1972 4K-bit devices were being designed, progressing through 16K and 64K, and now 256K and 1-Megabit devices are being designed in 1982. The chip size been about the same for all of these. As the capacitor size is reduced, and the number of cells on a bit line is increased, the difficulty in reliably sensing the stored charge is drastically increased. One of the solutions which has been proposed is the use of tantalum capacitors instead of MOS capacitors. Tantalum oxide has a much higher dielectric coefficient, so the capacitance per unit area could be greatly increased, but the change in manufacturing process has not been worthwhile with prior cells. The limitations on the use of silicon oxide storage capacitors may be exceeded for the 1-Megabit dynamic RAM, however, and so a practical cell with tantalum capacitors may be demanded.
It is the principal object of this invention to provide an improved one-transistor dynamic read/write memory cell, more particularly improved storage capacitors for these cells. Another object is to provide an improved tantalum capacitor which may be manufactured compatibly with self-aligned silicon-gate semiconductor processing. A further object is to provide storage capacitors of greater capacitance per unit area for VLSI semiconductor devices.